The present invention relates to a semiconductor device.
As the degree of integration of semiconductor devices increases, devices such as a MOSFET used in the output stage are required to have a high drain voltage and a low ON resistance. To meet these demands, patent reference 1 (to be described later) discloses a device using a semiconductor substrate (SOI (Silicon On Insulator) substrate) having an insulating layer.
This conventional device realizes a high drain voltage and a low ON resistance. However, a junction area present between an n-type offset layer 7 and p-type high-resistance semiconductor layer 3 shown in FIG. 1 of this reference is large. This increases the output capacitance in this junction portion.
The following is the name of the reference disclosing this conventional semiconductor device.
Japanese Patent Publication No. 07-086580 
As described above, the conventional semiconductor device has the problem that the output capacitance cannot be reduced.